The problem of obtaining satisfactorily high yields of usable monolithic solid-state imagers becomes increasingly difficult with increase of the area of the monolithic semiconductor die on which the imager reposes. This is especially so in the case of back-illuminated CCD imagers. The monolithic semiconductor dies on which they are constructed are thinned from five hundred microns or so to ten microns or so, making them perhaps the most difficult semiconductor devices to manufacture. It is desirable to keep low the number of phases of clocking signal applied to the gate electrodes of CCD registers in a CCD imager in order to transfer charge. This not only simplifies clocking signal generation, but makes it easier to bus the various clocking signal phases across the surface of the imager. While clocking with two phases or with uni-phase variants of two-phase clocking has been used in CCD imager shift register operations, this requires differential doping of the surface of the semiconductor die to which one would prefer not to have resort, and these types of operation are more likely to fail owing to interelectrode shorts. Three-phase clocking of the registers in CCD imagers has accordingly come to be preferred. This is so even though four-phase clocking of the image and field storage registers of a field transfer type of CCD imager is known to provide for more accurate line interlace on alternate fields where such interlace is used. Such four-phase clocking is described as an alternative by W. F. Kosonocky in U.S. Pat. No. 3,932,775 issued Jan. 13, 1976, and entitled "INTERLACED READOUT OF CHARGE STORED IN A CHARGE COUPLED IMAGE SENSING ARRAY."
CCD area-array imagers commercially available have tended to be small with sensor arrays that have an eight millimeter diagonal being the present standard. But there has been a desire to increase the size of the sensor arrays to have an eleven millimeter diagonal, so that the optical systems developed for vidicons and commercially available at advantageous prices can be employed with solid state imagers. Redesigning standard field transfer CCD imagers using three-phase clocking to have a pixel size more than twenty microns on a side in their image registers, in order to provide eleven millimeter diagonal dimension for those image registers, results in an unacceptably noisy video signal. A person viewing a television picture based on the CCD imager output video signal can tolerate appreciable amounts of the random noise called Johnson noise or dark current noise, which arises from thermodynamic processes in the imager. As long as patterned noise accompanying the video signal is smaller than the random noise, the random noise will mask the presence of the patterned noise in the television picture insofar as person viewing it is concerned. Patterned noise that is not smaller than the random noise is (at least to the point where random noise is so small as to be indiscernible) readily discernible to the person viewing the television picture and is categorized as being unacceptable in level by CCD imager designers. CCD imagers using three-phase clocking and having a pixel size more than twenty microns long in the direction of charge transfer through the image register generate a type of patterned noise that exhibits itself as "grain" in a television display based on the video signal, which grain resembles that encountered in silver halide photography prints owing to the random crystalline structure in the silver halide films. This grain has been a difficult obstacle to solid-state imager designers seeking to use CCD imagers of types which perform photoconversion in the image register CCD's themselves, particularly imagers of those types having large-area image registers. To obtain large-area sensor arrays, then, solid-state imager designers have tended to favor MOS (metal-oxide-semiconductor) imagers or interline transfer type CCD imagers, where photoconversion is not done in the CCD portions of the imager.
In the U.S. Pat. No. 4,507,684, issued Mar. 26, 1985 by D. F. Battson, entitled "REDUCING GRAIN IN MULTI-PHASE-CLOCKED CCD IMAGERS", and assigned to RCA Corporation, it is pointed out that grain in field transfer type CCD imagers is attributable to a certain type of partitioning noise. This partitioning noise affects the electrons generated by photoconversion in regions under the image register gate electrodes held low in potential in a multi-phase image register. With increase in the lengths of the barriers between potential wells, electrons generated in the regions between potential wells are less likely to be influenced by fringing fields from the potential wells induced under gate electrodes held high in potential. Consequently, these electrons are more likely to be affected by local electric field perturbations and so depart from ending up, on average, in the potential well closest to their generation site. This departure is perceived as grain structure in the image output. Grain increases rapidly as the lengths of potential barriers induced under certain of the gate electrodes becomes longer; this accords with the electrostatic force between an electron and a potential well being inversely related to the square of the distance between them. In buried-channel CCD imagers D. F. Battson experimented with, grain increased rapidly as the length of potential barriers under gate electrodes held low was made longer than five microns.
The Battson teaching has been followed to keep pixel size no more than twenty microns or so in direction of charge transfer in the three-phase-clock field transfer type of CCD imager. The number of pixels in the charge transfer channels of the image register are determined by the number of active (or picture) "scan" lines in each television field, numbering 240 or so for standard broadcast television and television signals according to related standards. This has helped to maintain as standard the 8 mm diagonal image register now commonly used in commercially available CCD area imagers.
In certain applications it is unacceptable, or at least undesirable, to reduce pixel size in the CCD imager. In certain earth satellite cameras, for example, the CCD imager is preceded by a very-narrow-passband optical filter which reduces the spectrum of energy reaching the imager. To obtain reasonably high sensitivity, pixel sizes fifty microns square or so must be used.
The present inventors advocate a different approach to following the Battson teaching, which approach does not require reducing pixel size in order to keep grain under control. In fact pixel length can be increased well above thirty microns when increasing pixel size to get better sensitivity. Sensitivity is improved because the photoconversion response, being spatially unrelated, increases linearly with pixel area while dark current noise, not being spatially correlated, increases as the square root of pixel area. The inventors advocate using a number n of clocking phases more than four in CCD imagers having pixel dimensions longer than thirty microns in the direction of charge transfer. Where the gate electrodes receptive of one cycle of these n-phases of clocking signal are of substantially equal length, n should be at least equal to the pixel length in the direction of charge transfer divided by the maximum gate electrode length (e.g., five to ten microns) associated with acceptably low grain. With the number n of clock phases being larger, the proportion of the charge carriers subject to partitioning by a potential energy barrier can be reduced to 1/n. So gate electrode length can be increased somewhat from the maximum length for three phases associated with acceptably low grain. During image integration, no two adjacent gate electrodes are held equally low in potential at the same time, again to avoid the effect of excessive potential barrier length. These steps preserve the fringing field effects needed to avoid grain generation.
In addition to keeping grain acceptably low, the n&gt;4-phase clocking of the image register during field transfer intervals provides a larger charge handling capability for given pixel size and potential energy well depth than clocking in fewer phases does. This, as well as the improved sensitivity afforded by larger pixel size, facilitates larger dynamic range of the video signals from the field transfer CCD imager. At times in a three-phase-clocked register two of the three gate electrodes in each pixel must be simultaneously low, so charge can be held in a well no longer than one-third pixel length. In a clocked register clocked in n at least five phases, at times, two of the n gate electrodes in each pixel must be simultaneously low, so charge cannot be held in a well longer than (n-2)/n pixel length. This well can be three-fifths pixel length for n=5, two-thirds pixel length for n=6 and three-quarters pixel length for n=8, by way of examples. And, of course, n can be even to facilitate perfect line interlace when one interlaces the scan lines in alternate fields.
Transfer efficiency through a CCD imager with large area pixels can be improved by improving the number of clocking signal phases per pixel. The most important figure of merit for a charge-transfer device is commonly regarded as being the charge-transfer efficiency, denoted by .eta., which is the fraction of the original charge packet that is transferred from one storage site to the next. The fraction that is not transferred is denoted by .epsilon., the charge-transfer inefficiency, or charge-transfer loss. Since the potential well used to store and transfer minority carriers also serves to repel majority carriers, recombination is negligible. Thus, minority carriers are lost from the original charge packet only by being left behind (i.e., charge is either transferred or it is not). Thus, EQU .eta.+.epsilon.=1.
The effect of imperfect transfer efficiency is to erode the amplitude of the signal packet, so that after n transfers, the ratio of the signal level A.sub.n to the original level A.sub.o is given by EQU A.sub.n /A.sub.o =.eta..sup.n =(1-.epsilon.).
So A.sub.n /A.sub.o approximates exp(-.epsilon.n) for small values of .epsilon.. This seems to indicate that the number of clock phases per pixel should be decreased, rather than increased per the invention, but there is more to be considered.
Two different effects prevent the attainment of perfect efficiency--the time required to transfer the free charge in the packet from one site to the next and trapping effects. Several driving mechanisms cause the free charge to transfer, including charge repulsion, thermal diffusion, and drift in the externally applied fields (fringing fields). Charge-repulsion effects are unimportant after most (about 99%) of the charge has transferred, so that the limitations on device speed are essentially determined by either thermal diffusion or fringing field drift. Both of these mechanisms cause an exponential decay of charge under the transferring electrode. The magnitude of the time constants for this decay determines the efficiency that can be achieved at any particular clock frequency, since the clock frequency determines the time available for transfer.
The time constant for thermal diffusion can be estimated by simple physical arguments which indicate that this time is l.sup.2 /2.5D.
Charge transfer is also enhanced by carrier drift in the field induced by the externally applied gate voltages. The externally applied field is principally directed perpendicular to the motion of charge, but there is a component of field along the direction of motion. The calculation of these fringing fields involves a rather complex two-dimensional electrostatic problem generally requiring a numerical solution. The transit time (or decay time constant) for fringing-field drift is then given by ##EQU1## where l is the gate length in the transfer direction, .mu. is the carrier mobility, V is the gate voltage, and X.sub.ox is the thickness of the gate oxide. In addition, because the fringing-field time constant depends upon l.sup.3 s, the increase in speed over that possible with thermal diffusion increases as gate length is decreased. Also, fringing-field drift is relatively more important in buried-channel devices, since the channel is a greater distance from the gates, effectively increasing the X.sub.ox /l factor.
Trapping also occurs in buried-channel devices in mono-energetic bulk states. Since the number of states that participate in trapping is low, the effect is small. The number of trapping states per unit area is equal to the volume density times the distance over which signal charge resides in the channel. This distance is on the order of 1 .mu.m, so that 10.sup.12 states/cm.sup.3 would result in only about 10.sup.8 states/cm.sup.2 states effective in surface channel devices.
In designing the gate structure for a large pixel, then, it is desirable to reduce l to a small value and at the same time maximize the charge storage area by having as many as possible of the gates crossing the pixel biased for accumulation during the charge integration period. One must balance the improvement in transfer efficiency of this approach for given forward clocking frequency by the accumulatative effect of increasing the number of transfers in moving the charge from one pixel to another, to determine when increase in the number of gate electrodes per pixel is no longer advantageous.
While one can design the n&gt;4-phase clocked image register so that gate electrodes under which barrier potential is erected are short enough that there is sufficient fringing field to avoid partitioning noise as will generate unacceptably large "grain", and at the same time make the other gate electrodes longer, there is a reason for making the gate electrodes all of substantially the same length. Making the gate electrodes of different length reduces the speed at which the underlying charge channels can be clocked without adversely affecting transfer efficiency. It is desirable to transfer charge packets out of the image register as quickly as possible to keep transfer smear acceptably low despite the presence of bright objects in the radiant image received by the CCD imager.